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TOSHIBA Original CMOS 16-Bit Microcontroller
TLCS-900/L Series
TMP93PW32
Semiconductor Company
Preface
Thank you very much for making use of Toshiba microcomputer LSIs. Before use this LSI, refer the section, "Points of Note and Restrictions". Especially, take care below cautions.
**CAUTION** How to release the HALT mode Usually, interrupts can release all halts status. However, the interrupts = (NMI , INT0), which can release the HALT mode may not be able to do so if they are input during the period CPU is shifting to the HALT mode (for about 3 clocks of fFPH) with IDLE1 or STOP mode (IDLE2/RUN are not applicable to this case). (In this case, an interrupt request is kept on hold internally.) If another interrupt is generated after it has shifted to HALT mode completely, halt status can be released without difficulty. The priority of this interrupt is compare with that of the interrupt kept on hold internally, and the interrupt with higher priority is handled first followed by the other interrupt.
TMP93PW32
Low Voltage/Low Power CMOS
16-bit Microcontrollers
TMP93PW32F 1. Outline and Device Characteristics
The TMP93PW32 is OTP type MCU which includes 128-Kbyte One-time PROM. Using the adapter-socket (BM11132), you can write and verify the data for the TMP93PW32. The TMP93PW32F has the same pin-assignment as TMP93CS32 (Mask ROM type). Writing the program to Built-in PROM, the TMP93PW32 operates as the same way as the TMP93CS32. The memory map and capacity of built in ROM and RAM are different between TMP93CS32 and TMP93PW32. The TMP93PW32 has the PROM of 128 Kbytes and the RAM of 4 Kbytes, and the TMP93CS32 has the ROM of 64 Kbytes and the RAM of 2 Kbytes. Following figure shows each memory map.
000000H 000080H 000000H Internal I/O (128 bytes) 000080H Internal I/O (128 bytes) Internal RAM (2 Kbytes) 000880H
Internal RAM (4 Kbytes) 001080H
External memory External memory FE0000H Internal PROM (128 Kbytes) FFFF00H Interrupt vector table (256 bytes) FFFFFFH TMP93PW32 memory map FFFFFFH TMP93CS32 memory map FF0000H Internal ROM (64 Kbytes) FFFF00H Interrupt vector table (256 bytes)
Product No.
TMP93PW32F
ROM
OTP 128 Kbytes
RAM
4 Kbytes
Package
P-QFP64-1414-0.80A
Adapter Socket
BM11132
030619EBP1
* The information contained herein is subject to change without notice. * The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of TOSHIBA or others. * TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the "Handling Guide for Semiconductor Devices," or "TOSHIBA Semiconductor Reliability Handbook" etc.. * The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury ("Unintended Usage"). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer's own risk. * The products described in this document are subject to the foreign exchange and foreign trade laws. * TOSHIBA products should not be embedded to the downstream products which are prohibited to be produced and sold, under any law and regulations. * For a discussion of how the reliability of microcontrollers can be predicted, please refer to Section 1.3 of the chapter entitled Quality and Reliability Assurance/Handling Precautions.
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TMP93PW32
AN0 to AN2 (P50 to P52) AN3/ ADTRG (P53) AN4, AN5 (P54, P55) AVCC AVSS VREFH VREFL
900/L CPU 10-bit 6-channel AD converter XWA XBC XDE XHL XIX XIY XIZ XSP WA BC DE HL IX IY IZ SP 32 bits SR PC Interrupt controller F
VCC [1] VSS [2] OSC X1 X2 CLK
Clock controller
TXD0 (P60) RXD0 (P61) SCLK0/ CTS0 (P62) TXD1 (P63) RXD1 (P64) SCLK1/ CTS1 (P65)
Serial I/O (channel 0) SERIAL I/O (channel 1)
AM8/ AM16
EA RESET
ALE INT0 (P35)
NMI
WAIT (P70)
P71 Port 7 Watchdog timer 4-Kbyte RAM Port 0 8-bit timer (Timer 0) 8-bit timer (Timer 1) 8-bit timer (Timer 2) 8-bit timer (Timer 3) 128-Kbyte PROM INT4/TI4 (P42) INT5/TI5 (P43) TO4 (P44) INT6/TI6 (P45) INT7/TI7 (P46) TO6 (P47) 16-bit timer (Timer 4) 16-bit timer (Timer 5) Port 2 AD0 to AD7 (P00 to P07)
Port 1
AD8 to AD15/A8 to A15 (P10 to P17)
A0 to A7/A16 to A23 (P20 to P27)
RD (P30) WR (P31) HWR (P32)
Port 3
TO3 (P41)
Wait controller (3-block)
Note: The items in parentheses ( ) are the initial setting after reset.
Figure 1.1 TMP93PW32 Block Diagram
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TMP93PW32
2. Pin Assignment and Functions
The assignment of input/output pins for the TMP93PW32, their names and functions are described below.
2.1
Pin Assignment
Figure 2.1.1 shows pin assignment of the TMP93PW32F.
P35 (INT0) P32 (HWR) P31(WR) P30 (RD) P27 (A23/A7) P26 (A22/A6) P25 (A21/A5) P24 (A20/A4) P23 (A19/A3) P22 (A18/A2) P21 (A17/A1) P20 (A16/A0) P17 (AD15/A15) P16 (AD14/A14) P15 (AD13/A13) P14 (AD12/A12) 48 (TO3) P41 (TI4/INT4) P42 (TI5/INT5) P43 (TO4) P44 (TI6/INT6) P45 (TI7/INT7) P46 (TO6) P47 VREFH VREFL AVSS AVCC (AN0) P50 (AN1) P51 (AN2) P52 (AN3/ ADTRG ) P53 (AN4) P54 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 1
2
46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
47
TMP93PW32F QFP64 Top view
P13 (AD11/A11) P12 (AD10/A10) P11 (AD9/A9) P10 (AD8/A8) P07 (AD7) P06 (AD6) P05 (AD5) P04 (AD4) P03 (AD3) P02 (AD2) P01 (AD1) P00 (AD0) ALE VSS VCC
RESET
Figure 2.1.1 Pin Assignment (64-pin QFP)
(TXD0) P60 (RXD0) P61 (SCLK0/CTS0) P62 (TXD1) P63 (RXD1) P64 (SCLK1/CTS1) P65 (WAIT) P70 P71 VSS CLK AM8/AM16 X1 X2
(AN5) P55
NMI
93PW32-3
EA
3 4 5 6 7 8 9 10 11 12 13 14 15 16
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TMP93PW32
2.2
Pin Names and Functions
The TMP93PW32 has MCU mode and PROM mode. (1) Table 2.2.1 and Table 2.2.2 show pin function of TMP93PW32 in MCU mode. Table 2.2.1 Pin Names and Function (1/2) Pin Name Number of Pins
8
I/O
I/O 3 states I/O 3 states Output I/O
Functions
Port 0: I/O port that allows selection of I/O on a bit basis Address/Data (lower): Bits 0 to 7 for address/data bus Port 1: I/O port that allows selection of I/O on a bit basis Address/Data (upper): Bits 8 to 15 for address/data bus Address: Bits 8 to 15 for address bus Port 2: I/O port that allows selection of I/O on a bit basis (with pull-up resistor) Address: Bits 0 to 7 for address bus Address: Bits 16 to 23 for address bus Port 30: Output port Read: Strobe signal for reading external memory Port 31: Output port Write: Strobe signal for writing data on pins AD0 to AD7 Port 32: I/O port (with pull-up resistor) High write: Strobe signal for writing data on pins AD8 to AD15 Port 35: I/O port Interrupt request pin 0: Interrupt request pin with programmable level/rising edge Port 41: I/O port PWM output 3: 8-bit PWM timer 3 output Port 42: I/O port Timer input 4: Timer 4 count/capture trigger signal input Interrupt request pin 4: Interrupt request pin with programmable rising/falling edge Port 43: I/O port Timer input 5: Timer 4 count/capture trigger signal input Interrupt request pin 5: Interrupt request pin with rising edge Port 44: I/O port Timer output 4: Timer 4 output pin Port 45: I/O port Timer input 6: Timer 5 count/capture trigger signal input Interrupt request pin 6: Interrupt request pin with programmable rising/falling edge Port 46: I/O port Timer input 7: Timer 5 count/capture trigger signal input Interrupt request pin 7: Interrupt request pin with rising edge Port 47: I/O port Timer output 6: Timer 5 output pin
P00 to P07 AD0 to AD7 P10 to P17 AD8 to AD15 A8 to A15 P20 to P27 A0 to A7 A16 to A23 P30
RD
8
8
Output Output Output Output Output Output I/O Output I/O Input I/O Output I/O Input Input
1 1 1
P31
WR
P32
HWR
P35 INT0 P41 TO3 P42 TI4 INT4 P43 TI5 INT5 P44 TO4 P45 TI6 INT6 P46 TI7 INT7 P47 TO6
1
1
1
I/O 1 Input Input 1 I/O Output I/O 1 Input Input
I/O 1 Input Input 1 I/O Output
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Table 2.2.2 Pin Names and Function (2/2) Pin Name
P50 to P52, P54, P55 AN0 to AN2, AN4, AN5 P53 AN3
ADTRG
Number of Pins
5
I/O
Input Input Input
Functions
Port 50 to Port 52, Port 54, Port 55: Input port Analog input: Analog signal input for AD converter Port 53: Input Port Analog input: Analog signal input for AD converter AD converter external start trigger input Port 60: I/O port (with pull-up resistor) Serial send data 0 Port 61: I/O port (with pull-up resistor) Serial receive data 0 Port 62: I/O port (with pull-up resistor) Serial clock I/O 0 Serial data send enable 0 (clear to send) Port 63: I/O port (with pull-up resistor) Serial send data 1 Port 64: I/O port (with pull-up resistor) Serial receive data 1 Port 65: I/O port (with pull-up resistor) Serial clock I/O 1 Serial data send enable 1 (clear to send) Port 70: I/O port (High current output available) Wait: Pin used to request CPU bus wait (It is active in (1 + N) waits mode. Set by the bus-width/wait control register.) Port 71: I/O port (High current output available) Non-maskable interrupt request pin: Interrupt request pin with falling edge. Can also be operated at falling and rising edges by program. Clock output: Outputs "fSYS / 2" Clock. Pulled-up during reset. Can be disabled for reducing noise. "1" should be inputted with TMP93PW32. Address mode: Selects external data bus width. "1" should be inputted. The data bus width for external access is set by chip select/wait control register and Port 1 control register. Address Latch Enable Can be disabled for reducing noise. Reset: Initializes TMP93PW32. (with pull-up resistor) Pin for high level reference voltage input to AD converter Pin for low level reference voltage input to AD converter Power supply pin for AD converter GND pin for AD converter (0 V) Oscillator connecting pin Oscillator connecting pin Power supply pin GND pin (All VSS pins are connected to the GND (0 V).)
1
Input Input I/O Output I/O Input I/O I/O Input I/O Output I/O Input I/O I/O Input I/O
P60 TXD0 P61 RXD0 P62 SCLK0
CTS0
1 1
1
P63 TXD1 P64 RXD1 P65 SCLK1
CTS1
1 1
1
P70
WAIT
1 1 1
Input I/O Input
P71
NMI
CLK 1
EA
Output
1 1
Input Input
AM8/ AM16
ALE
RESET
1 1 1 1 1 1 1 1 1 2
Output Input Input Input Input Input Input Output Input Input
VREFH VREFL AVCC AVSS X1 X2 VCC VSS
Note:
Built-in pull-up resistors can be released from the pins other than the RESET pin by software.
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TMP93PW32
(2) PROM mode Table 2.2.3 shows pin function of the TMP93PW32 in PROM mode. Table 2.2.3 Pin Name and Function of PROM Mode Pin Function
A7 to A0 A15 to A8 A16 D7 to D0
CE OE PGM
Number of Pins
8 8 1 8 1 1 1 1 2 3
Input/ Output
Input Input Input I/O Input Input Input Power supply Power supply Power supply
Function
Pin Name (MCU Mode)
P27 to P20
Memory address of program Memory data of program Chip enable Output control Program control 12.75 V/5 V (Power supply of program) 6.25 V/5 V 0V
P17 to P10 P71 P07 to P00 P32 P30 P31
EA
VPP VCC VSS
VCC, AVCC VSS, AVSS
Pin Function
P60
RESET
Number of Pins
1 1 1 1 1 1 6
Input/ Output
Input Input Input Output Input Output Input
Disposal of Pin
Fix to low level (security pin) Fix to low level (PROM mode) Open Self oscillation with resonator Fix to high level
CLK ALE X1 X2 P65 to P61 AM8/ AM16 P35 P47 to P41 P55 to P50 P70 VREFH VREFL
NMI
18
I/O
Open
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TMP93PW32
3.
Operation
This section describes the functions and basic operational blocks of the TMP93PW32. The TMP93PW32 has PROM in place of the mask ROM which is included in the TMP93CS32. The other configuration and functions are the same as the TMP93CS32. Regarding the functions of the TMP93PW32 (Not described), see the part of TMP93CS32. The TMP93PW32 has two operational modes: MCU mode and PROM mode.
3.1
MCU Mode
(1) Mode-setting and function The MCU mode is set by opening the CLK pin (Pin open). In the MCU mode, the operation is same as TMP93CS32 except the followings. (2) Memory map The memory map of TMP93PW32 is not same as that of TMP93CS32. Figure 3.1.1 shows the memory map in MCU mode. Figure 3.1.2 show that in PROM mode.
000000H 000080H Internal RAM (4 Kbytes) 001080H 00000H Internal I/O (128 bytes)
Internal PROM (128 Kbytes) External memory
FE0000H Internal PROM (128 Kbytes) FFFF00H Interrpt vector table (256 bytes) FFFFFFH ( = Internal area)
1FFFFH
Figure 3.1.1 Memory Map in MCU Mode
Figure 3.1.2 Memory Map in PROM Mode
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TMP93PW32
(3) Care point of bus width/wait controller The built in RAM capacity of the TMP93PW32 is larger than that of the TMP93CS32, therefore the following point is different about the accessing area of WAITC1. Setting WAITC1 to "00"
TMP93PW32 1080H to 7FFFH TMP93CS32 880 to 7FFFH
WAITC0 and WAITC2 addressing area are the same as TMP93CS32.
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TMP93PW32
3.2
PROM Mode
(1) Mode setting and function PROM mode is set by setting the RESET and CLK pins to the "L" level. The programming and verification for the internal PROM is achieved by using a general EPROM programmer with the adaptor socket. 1. Preparation of OTP adaptor BM11132: for TMP93PW32 2. Setting of OTP adaptor The switch (SW1) is set to N side. 3. Setting of PROM writer i) Set PROM type to TC 571000D. Size: 1 Mbits (128 K x 8 bits) VPP: 12.75 V tPW: 100 s Electric signature mode: none ii) Data transmittion In TMP93PW32F, PROM is placed on addresses 00000 to 1FFFFH in PROM mode, and addresses FE0000H to FFFFFFH in MCU mode. Therefore data should be transferred to addresses 00000 to 1FFFFH in PROM mode using the object converter (tuconv) or the block transfer mode. (See instruction manual of PROM programmer.) iii) Setting of the program address Start address: 00000H End address: 1FFFFH 4. Programming Program and verify according to operating process of PROM programmer.
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TMP93PW32
Figure 3.2.1 shows the setting of the pins in PROM mode.
VPP (12.75 V/5 V)
EA
VCC AVCC, VCC P30 P32 P31 P71 P17 to P10 P27 to P20 P07 to P00
RESET OE CE PGM
A16 to A0
D7 to D0
CLK VCC
X1
P65 to P61 AM8/ AM16
X2 VSS AVSS
P60
SECURITY
For other pins, refer to the section on pin functions (Table 2.2.2 ). * Use the 10 MHz resonator in case of programming and verification by a general PROM programmer.
Figure 3.2.1 PROM Mode Pin Setting (2) Caution for electric signature The TMP93PW32 dose not support the electric signature mode (hereinafter referred to as "signature"). If PROM programmer used the signature, the device would be damaged because of applying voltage of 12 0.5 V to pin 9 (A9) of the address. Please use without setting the signature. (3) Program mode All bits of the TMP93PW32 are "1" when delivered (the erase state). Data "0" is written in the necessary bit location during program operating. Writing function can be operated at VPP = 12.5 V, OE = VIH, CE = VIL. Built-in one time PROM can be written in any sequence. It is possible to write only special address. (4) Adopter socket (BM11132) BM11132 is the adapter sockets to write data into the TMP93PW32F. The TMP93PW32F has built-in one time PROM using a general EPROM programmer. (5) Program storing area of PROM mode The TMP93PW32 has the program space (FE0000H to FFFFFFH) of 128 Kbytes. The address 00000H to 1FFFFH of PROM mode equals to the address FE0000H to FFFFFFH of MCU mode.
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(6) Program write setting method using a general PROM programmer PROM to be prepared should equal to TC571000D functions. 1. 2. 3. 4. 5. 6. Set the switch (SW1) of BM11132 (hereinafter referred to as "adapter") to the program side (NOR) (Note 1). Connect MCU to the adapter (Note 2). Connect the adapter to PROM programmer (Note 2). Set the PROM type of PROM programmer to TC571000D. Set the start address for writing PROM to 00000H, and the end address to 1FFFFH (Note 3). Writing to built-in one time PROM and verifying should be operated according to the operation procedures of PROM programmer.
Note 1: If data is written to built-in one time PROM without setting the switch (SW1) to the program side, the device would be damaged. Note 2: Please set with the first pin of the adapter and that of PROM programmer socket matched. If the first pin is conversely set, MCU or programmer would be damaged. Note 3: If data "0" is written to the address which is over 1FFFFH, the contents of the original program would be damaged because of writing "0" to the addresses 00000H to 1FFFFH. (7) Programming flow chart The programming mode is set by applying 12.75 V (Programming voltage) to the VPP pin when the following pins are set as follows, (VCC: 6.25 V, RESET : "L" level, CLK: "L" level). While address and data are fixed and CE pin is set to "L" level, 0.1 ms of "L" level pulse is applied to PGM pin to program the data. Then the data in the address is verified. If the programmed data is incorrect, another 0.1 ms pulse is applied to PGM pin. This programming procedure is repeated until correct data is read from the address. (25 times maximum) Subsequently, all data are programmed in all addresses. The verification for all data is done under the condition of VPP = VCC = 5 V after all data were written. Figure 3.2.2 shows the programming flow chart.
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Start
VCC = 6.25 V 0.25 V VPP = 12.75 V 0.25 V
Address = Start address
X=0
Program 0.1 ms pulse
X=X+1
X > 25? No Error Address = Address + 1 No Verify OK Last address? Yes VCC = 5 V VPP = 5 V
Yes
Read all data OK Pass
Error
Failure
Figure 3.2.2 Flow Chart (High-speed program writing)
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TMP93PW32
(8) Security bit The TMP93PW32 has a security bit in PROM cell. If the security bit is programmed to "0", the content of the PROM is disable to be read (FFH data) in PROM mode. (How to program the security bit.) The difference from the programming procedures described in section 3.2 (1) are follows. 1. Setting OTP adaptor Set the switch (SW1) to S side. 2. Setting PROM programmer i) Transferring the data ii) Setting of programming address The security bit is in bit0 of address 00000H. Set the start address 00000H and the end address 00000H. Set the data FEH at the address 00000H.
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4.
4.1
Electrical Characteristics
Absolute Maximum Ratings (TMP93PW32)
Parameter
Power supply voltage Input voltage Output current (per 1 pin) P7 Output current (per 1 pin) except P7 Output current (total) Output current (total) Power dissipation (Ta = 85C) Soldering temperature (10 s) Storage temperature Operating temperature
"X" used in an expression shows a cycle of clock fFPH. If a clock gear or a low speed oscillator is selected, a value of "X" is different. The value as an example is gear = 1/fc (SYSCR1 = "000").
Symbol
VCC VIN IOL1 IOL2 IOL IOH PD TSOLDER TSTG TOPR
EA pin
Rating
-0.5 to 6.5 Except EA pin -0.5 to VCC + 0.5 -0.5 to 14.0 20 2 120 -80 350 260 -65 to 150 -40 to 85
Unit
V
mA
mW C
Note:
The absolute maximum ratings are rated values which must not be exceeded during operation, even for an instant. Any one of the ratings must not be exceeded. If any absolute maximum rating is exceeded, a device may break down or its performance may be degraded, causing it to catch fire or explode resulting in injury to the user. Thus, when designing products which include this device, ensure that no absolute maximum rating value will ever be exceeded.
4.2
DC Characteristics
Ta = -40 to 85C Parameter Symbol
VCC
Condition
fc = 4 to 20 MHz fc = 4 to 12.5 MHz VCC 4.5 V VCC < 4.5 V
Min
4.5 2.7
Typ. (Note)
Max
5.5 0.8 0.6 0.3 VCC 0.25 VCC 0.3 0.2 VCC
Unit
Power supply voltage AVCC = VCC AVSS = VSS = 0 V Input low voltage AD0 to AD15 Port 2 to 7 (except P35)
RESET , NMI , INT0 EA , AM8/ AM16
VIL VIL1 VIL2 VIL3 VIL4 VIH VIH1 VIH2 VIH3 VIH4 VOL IOL7 VOH1
-0.3 VCC = 2.7 to 5.5 V
X1 AD0 to AD15 Port 2 to 7 (except P35)
RESET , NMI , INT0 EA , AM8/ AM16
V
Input high voltage
VCC 4.5 V VCC < 4.5 V
2.2 2.0 0.7 VCC 0.75 VCC VCC - 0.3 0.8 VCC VCC + 0.3
VCC = 2.7 to 5.5 V
X1
Output low voltage Output low current (P7)
IOL = 1.6 mA (VCC = 2.7 to 5.5 V) VOL = 1.0 V (VCC = 5 V 10%) (VCC = 3 V 10%) 16 7 2.4
0.45 mA
Output high voltage VOH2
IOH = -400 A (VCC = 3 V 10%) IOH = -400 A (VCC = 5 V 10%)
V 4.2
Note: Typical values are for Ta = 25C and VCC = 5 V unless otherwise noted.
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Parameter
Darlington drive current (8 output pins max) Input leakage current Output leakage current Power down voltage (at STOP, RAM back up)
RESET
Symbol
IDAR (Note2) ILI ILO VSTOP
Condition
VEXT = 1.5 V REXT = 1.1 k (VCC = 5 V 10% only) 0.0 VIN VCC 0.2 VIN VCC - 0.2 VIL2 = 0.2 VCC, VIH2 = 0.8 VCC VCC = 5.5 V VCC = 4.5 V VCC = 3.3 V VCC = 2.7 V fc = 1 MHz
Min
-1.0
Typ. (Note1)
Max
-3.5
Unit
mA A V
0.02 0.05 2.0 45 50 70 90
5 10 6.0 130 160 280 400 10
pull-up resistor Pin capacitance Schmitt width RESET , NMI , INT0 Programmable pull-up resistor NORMAL (Note 3) RUN IDLE2 IDLE1 NORMAL (Note 3) RUN IDLE2 IDLE1 STOP
RRST
k
CIO VTH
pF V
0.4 VCC = 5.5 V 45 50 70 90
1.0 130 160 280 400 25 30 27 17 5 11 10 6 1.8 10 0.2 20 50 22 13 3.4 8.0 7.0 4.2 1.2
RKH
VCC = 4.5 V VCC = 3.3 V VCC = 2.7 V VCC = 5 V 10% fc = 20 MHz
k
mA
ICC
VCC = 3 V 10% fc = 12.5 MHz (Typ.: VCC = 3.0 V) Ta 50C Ta 70C Ta 85C VCC = 2.7 V to 5.5 V
A
Note 1: Typical values are for Ta = 25C and VCC = 5 V unless otherwise noted. Note 2: IDAR is guranteed for total of up to 8 ports. Note 3: ICC measurement conditions (NORMAL): Only CPU is operational; output pins are open and input pins are fixed. (Reference) Definition of IDAR
REXT IDAR
VEXT
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4.3
AC Electrical Characteristics
(1) VCC = 5 V 10% Variable Min
50 2x - 40 0.5x - 20 1.5x - 70 0.5x - 15 0.5x - 20 x - 40 0.5x - 25 0.5x - 20 x - 25 1.5x - 50 0.5x - 25 3.0x - 55 3.5x - 65 2.0x - 60 2.0x - 40 0 x - 15 2.0x - 40 2.0x - 55 0.5x - 15 3.5x - 90 3.0x - 80 2.0x + 0 2.5x - 120 2.5x + 50 200 206 200 125 36 175 200 85 0 48 85 70 16 129 108 100 5
No.
Parameter
Symbol
tOSC tCLK tAK tKA tAL tLA tLL tLC tCL tACL tACH tCA tADL tADH tRD tRR tHR tRAE tWW tDW tWD
(1 + n) WAIT mode (1 + n) WAIT mode (1 + n) WAIT mode
16 MHz Min
62.5 85 11 24 16 11 23 6 11 38 44 6 133 154 65
20 MHz Min
50 60 5 5 10 5 10 0 5 25 25 0 95 110 40 60 0 35 60 45 10 85 70
Max
31250
Max
Max
Unit
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
1 Osc. period (= x) 2 CLK pulse width 3 A0 to A23 valid CLK hold 4 CLK valid A0 to A23 hold 5 A0 to A15 valid ALE fall 6 ALE fall A0 to A15 hold 7 ALE high pulse width 8 ALE fall RD / WR fall 9 RD / WR rise ALE rise 10 A0 to A15 valid RD / WR fall 11 A0 to A23 valid RD / WR fall 12 RD / WR rise A0 to A23 hold 13 A0 to A15 valid D0 to D15 input 14 A0 to A23 valid D0 to D15 input 15 RD fall D0 to D15 input 16 RD low pulse width 17 RD rise D0 to D15 hold 18 RD rise A0 to A15output 19 21
WR low pulse width
20 D0 to D15 valid WR rise
WR rise D0 to D15 hold
22 A0 to A23 valid WAIT input 23 A0 to A15 valid WAIT input 24 RD / WR fall WAIT hold 25 A0 to A23 valid Port input 26 A0 to A23 valid Port hold 27
WR rise Port valid
tAWH tAWL tCW tAPH tAPH2 tCP
AC measuring conditions * * Output level: High 2.2 V/Low 0.8 V, CL = 50 pF (However CL = 100 pF for AD0 to AD15, A0 to A23, ALE, RD , WR , HWR , CLK) Input level: High 2.4 V/Low 0.45 V (AD0 to AD15) High 0.8 x VCC/Low 0.2 x VCC (Except for AD0 to AD15)
93PW32-16
2004-02-10
TMP93PW32
(2) VCC = 3 V 10% No. Parameter Symbol
tOSC tCLK tAK tKA tAL tLA tLL tLC tCL tACL tACH tCA tADL tADH tRD tRR tHR tRAE tWW tDW
(1 + n) WAIT mode (1 + n) WAIT mode (1 + n) WAIT mode
Variable Min
80 2x - 40 0.5x - 30 1.5x - 80 0.5x - 35 0.5x - 35 x - 60 0.5x - 35 0.5x - 40 x - 50 1.5x - 50 0.5x - 40 3.0x - 110 3.5x - 125 2.0x - 115 2.0x - 40 0 x - 25 2.0x - 40 2.0x - 120 0.5x - 40 3.5x - 130 3.0x - 100 2.0x + 0 2.5x - 195 2.5x + 50 200
12.5 MHz Min
80 120 10 40 5 5 20 5 0 30 70 0 130 155 45 120 0 55 120 40 0 150 140 160 5 250 200
Max
31250
Max
Unit
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
1 Osc. period (= x) 2 CLK pulse width 3 A0 to A23 valid CLK hold 4 CLK valid A0 to A23 hold 5 A0 to A15 valid ALE fall 6 ALE fall A0 to A15 hold 7 ALE high pulse width 8 ALE fall RD / WR fall 9 RD / WR rise ALE rise 10 A0 to A15 valid RD / WR fall 11 A0 to A23 valid RD / WR fall 12 RD / WR rise A0 to A23 hold 13 A0 to A15 valid D0 to D15 input 14 A0 to A23 valid D0 to D15 input 15 RD fall D0 to D15 input 16 RD low pulse width 17 RD rise D0 to D15 hold 18 RD rise A0 to A15 output 19 21
WR low pulse width
20 D0 to D15 Valid WR rise
WR rise D0 to D15 hold
tWD tAWH tAWL tCW tAPH tAPH2 tCP
22 A0 to A23 valid WAIT input 23 A0 to A15 valid WAIT input 24 RD / WR fall WAIT hold 25 A0 to A23 valid Port input 26 A0 to A23 valid Port hold 27
WR rise Port valid
AC measuring conditions * Output level: High 0.7 x VCC/Low 0.3 x VCC, CL = 50 pF * Input level: High 0.9 x VCC/Low 0.1 x VCC
93PW32-17
2004-02-10
TMP93PW32
(3) Read cycle
tOSC X1
tCLK CLK tAK A0 to A23 tAWH tAWL
WAIT
tKA
tCW
tAPH tAPH2 Port input (Note) tADH
RD
tRR tRD
tCA
tACH tACL tLC
tRAE tHR D0 to D15 tCL
tADL
AD0 to AD15 tAL ALE tLL
A0 to A15 tLA
Note: Since the CPU accesses the internal area to read data from a port, the control signals of external pins such as RD and CS are not enabled. Therefore, the above waveform diagram should be regarded as depicting internal operation. Please also note that the timing and AC characteristics of port input/output shown above are typical representation. For details, contact your local Toshiba sales representative.
93PW32-18
2004-02-10
TMP93PW32
(4) Write cycle
X1
CLK
A0 to A23
WAIT
Port output (Note) tWW
WR , HWR
tCP
tDW AD0 to AD15 A0 to A15 D0 to D15
tWD
ALE
Note: Since the CPU accesses the internal area to write data to a port, the control signals of external pins such as WR and CS are not enabled. Therefore, the above waveform diagram should be regarded as depicting internal operation. Please also note that the timing and AC characteristics of port input/output shown above are typical representation. For details, contact your local Toshiba sales representative.
93PW32-19
2004-02-10
TMP93PW32
4.4
Serial Channel Timing
(1) I/O interface mode a. SCLK input mode
Symbol tSCY tOSS tOHS tHSR
Parameter
SCLK cycle Output data Rising/falling edge of SCLK SCLK rising/falling edge Output data hold SCLK rising/falling edge Input data hold
Variable Min
16x tSCY/2 - 5x - 50 5x - 100 0 tSCY - 5x - 100
12.5 MHz Max Min
1.28 s 190 300 0 780
20 MHz Min
0.8 s 100 150 0 450
Max
Max
Unit
ns ns ns ns ns
SCLK rising/falling edge Effective data input tSRD
Note: SCLK rising/falling timing ; SCLK rising in the rising mode of SCLK, SCLK falling in the falling mode of SCLK. b. SCLK output mode
Symbol tSCY tOSS tOHS tHSR tSRD
Parameter
SCLK cycle (programmable) Output data SCLK rising edge SCLK rising edge Output data hold SCLK rising edge Input data hold SCLK rising edge Effective data input SCLK Output mode /Input rising edge mode SCLK (Input falling edge mode)
Variable Min
16x tSCY - 2x - 150 2x - 80 0 tSCY - 2x - 150
12.5 MHz Max
8192x
20 MHz Min
0.8 s
Min
970 80 0
Max
Max
409.6 s
Unit
ns ns ns ns
1.28 s 655.36 s
550 20 0 970 550
ns
tSCY
tOSS Output data TXD Input data RXD 0
tOHS 1 tSRD 0 Valid 1 Valid tHSR 2 Valid 3 Valid 2 3
(2) UART mode (SCLK0 and SCLK1 are external input) Parameter
SCLK cycle SCLK low level pulse width SCLK high level pulse width Symbol tSCY tSCYL tSCYH
Variable Min
4x + 20 2x + 5 2x + 5
12.5 MHz Max Min
340 165 165
20 MHz Min
220 105 105
Max
Max
Unit
ns ns ns
93PW32-20
2004-02-10
TMP93PW32
4.5
AD Conversion Characteristics
AVCC = VCC, AVSS = VSS Parameter Symbol
VREFH VREFL VAIN IREF (VREFL = 0 V) - VCC = 5 V 10% VCC = 3 V 10% VCC = 2.7 to 5.5 V VCC = 5 V 10% VCC = 3 V 10%
Power Supply
VCC = 5 V 10% VCC = 3 V 10% VCC = 5 V 10% VCC = 3 V 10%
Min
VCC - 1.5 VCC - 0.2 VSS VSS VREFL
Typ.
VCC VCC VSS VSS 0.5 0.3 0.02 1.0 1.0
Max
VCC VCC VSS + 0.2 VSS + 0.2 VREFH 1.5 0.9 5.0 3.0 5.0
Unit
Analog reference voltage (+) Analog reference voltage (-) Analog input voltage range Analog current for analog reference voltage = 1 = 0 Error (except quantization errors)
V
mA A LSB
Note 1: 1LSB = (VREFH - VREFL)/210 [V] Note 2: The operation above is guaranteed for fFPH 4 MHz. Note 3: The value ICC includes the current which flows through the AVCC pin.
4.6
Event Counter Input Clock (External Input Clock: TI4, TI5, TI6, TI7)
Parameter
Symbol tVCK tVCKL tVCKH
Variable Min
8X + 100 4X + 40 4X + 40
12.5 MHz Max Min
740 360 360
20 MHz Min
500 240 240
Max
Max
Unit
ns ns ns
Clock cycle Low level clock pulse width High level clock pulse width
4.7
Interrupt and Capture Operation
(1) NMI and INT0 Interrupts Parameter
Symbol tINTAL tINTAH
Variable Min
4X 4X
12.5 MHz Max Min
320 320
20 MHz Min
200 200
Max
Max
Unit
ns ns
NMI , INT0 low level pulse width
NMI , INT0 high level pulse width
(2) INT4 to INT7 Interrupts and Capture Parameter
INT4 to INT7 low level pulse width INT4 to INT7 high level pulse width Symbol tINTBL tINTBH
Variable Min
4X + 100 4X + 100
12.5 MHz Max Min
420 420
20 MHz Min
300 300
Max
Max
Unit
ns ns
93PW32-21
2004-02-10
TMP93PW32
4.8
Read Operation in PROM Mode
DC/AC characteristics Ta = 25 5C, VCC = 5 V 10% Parameter Symbol
VPP VIH1 VIL1 tACC
Condition
- - - CL = 50 pF
Min
4.5 2.2 -0.3 -
Max
5.5 VCC + 0.3 0.8 2.25 TCYC +
Unit
V ns
VPP read voltage Input high voltage (A0 to A16, CE , OE , PGM ) Input low voltage (A0 to A16, CE , OE , PGM ) Address to output delay
TCYC = 400 ns (10 MHz Clock) = 200 ns A0 to A16
CE
OE
PGM
D0 to D7
tACC Data output
93PW32-22
2004-02-10
TMP93PW32
4.9
Program operation in PROM Mode
DC/AC characteristics Ta = 25 5C, VCC = 6.25 V 0.25 V Parameter Symbol
VPP VIH VIL ICC IPP tPW
Condition
- - - fc = 10 MHz VPP = 13.00 V CL = 50 pF
Min
12.50 2.6 -0.3 - - 0.095
Typ.
12.75
Max
13.00 VCC + 0.3 0.8 50 50
Unit
Programming supply voltage Input high voltage (D0 to D7, A0 to A16, CE , OE , PGM ) Input low voltage (D0 to D7, A0 to A16, CE , OE , PGM ) VCC supply current VPP supply current
PGM program pulse width
V
mA ms
0.1
0.105
A0 to A16
CE OE
D0 to D7
PGM
Unknown
Data-in stable tPW
Output data valid
VPP
Note 1: The power supply of VPP (12.75 V) must be set power on at the same time or the later time for a power supply of VCC and must be clear power on at the same time or early time for a power supply of VCC. Note 2: The pulling up/down device on condition of VPP = 12.75 V suffer a damage for the device. Note 3: The maximum spec of VPP pin is 14.0 V. Be carefull a overshoot at the program writing.
93PW32-23
2004-02-10
TMP93PW32
5. Package Dimensions
P-QFP64-1414-0.80A Unit: mm
93PW32-24
2004-02-10

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